The present invention relates to a differential ECL (Emitter Coupled Logic circuit), and more particularly to that provided with a clamp circuit for preventing malfunction caused when its input terminals are left open.
By way of example, a prior art of the differential ECL having a clamp circuit is described with reference to a circuit diagram of FIG. 4 which illustrates a differential ECL disclosed in a Japanese patent application laid open as a Provisional Publication No. 10727/'89.
The differential ECL of FIG. 4 has a differential circuit 1 comprising;
a constant current source Ics connected between a node N and a negative supply VEE, PA1 first and second resistors R11 and R12, each having an end connected to a positive supply GND, and PA1 first and second transistors Q11 and Q12, each having a collector connected to the other ends of the first and the second resistors R11 and R12, an emitter connected to the node N, and a base supplied with one of complementary input signals IN and IN, and PA1 a clamp circuit 40 comprising a serial connection of three diodes D21, D22 and D23 provided between the node N and the positive supply GND.
FIG. 5 is a graphic chart illustrating potential VE of the node N changing in accordance with the complementary input signals IN and IN.
When the bases of the first and the second transistors Q11 and Q12 are supplied with the complementary input signals IN and IN of ordinary potential level for the ECL, the clamp circuit 40 remains OFF with no current flowing through the three diodes D21, D22 and D23, as follows.
HIGH and LOW level of the complimentary input signals being -0.9V, -1.7V, respectively, and forward biases of the diodes or transistors being 0.8V, potential VE of the node N is represented as VE=min(IN, IN)-0.8V, min(IN, IN) denoting lower potential of the complementary input signals IN and IN, which remains over -2.4V, and potential difference between the node N and the positive supply GND does not become more than three times of the forward bias.
When both the bases become open with no base-current supplied, the first and the second transistors Q11 and Q12 become OFF and the potential VE of the node N falls until clamped by the clamp circuit 40, the three diodes D21, D22 and D23 becoming ON. In this case, output signals OUT and OUT from collectors of the first and the second transistors Q11 and Q12 become both at HIGH level, current of the constant current source Ics flowing through the clamp circuit 40.
Thus, the malfunction resulting from the constant current source Ics being cut off from the power supply is prevented in the prior art of FIG. 4. However, there still remains a disadvantage in that output logic to be supplied to next differential logic circuit is undetermined when input terminals of the differential ECL of FIG. 4 are left open, because output signals to be complementary become both at HIGH level with no current flowing through neither of the first and the second resistors R11 and R12.